Silicon photonic devices are very sensitive to process variation, and it is important for circuit designers that they can predict the effect of this variability during the design phase, and optimize their design for both performance and yield. This requires an accurate predictive model of the spatial variations induced by the fabrication process. We present in this paper a method to extract a granular map of the line width and thickness variation on a silicon photonics wafer. We propose a hierarchical model to separate the layout-dependent and location-dependent systematic process variation from the random process variation on different spatial levels. We identify the relative contributions to width and thickness variations and use this to construct a synthetic model for virtual wafers that can be used to analyze the effect on circuit behavior and eventually predict the yield of photonic circuits after fabrication. We observe that the main contribution to waveguide width and thickness variations are systematic, and that die-scale systematic line width variation is correlated with local pattern density.
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